What is characterization limit?
What is characterization andwhat do we understand by its limit? Also what are the differences between the spice generated after characterization and CDL that we are provided for LVS ?
View ArticleVerilog AMS
I need to design a comparator through Verilog AMS. Could anyone guide me on how to approach? I am new to the language and don't know how to model analog systems like comparators/ op amps/sample and...
View Articleschematic from netlist
Hi....... How to import schematic from netlist in cadence.............? i completetd this task upto MOSFET but i found diificulties in resistor and capacitor conversion to schematic. Can anyone help me...
View Articleverilog code, please rectify errors
Verilog Code for floating point adder: Procedure for this stage: Take the Two 7-bit exponential binary numbers (a and b) and subtracting them. Let the result be named as ‘ediff’. We have to shift...
View ArticleNeed to know the Inputs at each stage in Physical Design? Please respond...
Kindly give me an outline about inputs in each stage i,e: Simulation, Floor Planning, Placement, CTS, Routing. of PD
View Articledrc rule
Can anyone please help me to understand the below drc rule :- ((PO interact (CO AND FGC)) interact (CO NOT FGC))
View ArticleLayout extraction
Hello All, How can we extract the details like --> I want the list of pairs of nets which one is the closest net is going to be manufactured from layout? How can I get this information. Thanks &...
View Articlevoltage domain crosing interface(VDCI)
can any one tell me about the timing challenges in VDCI ?
View ArticleGDS back to DEF/ MW DB
Hi, Here is a problem. Please bring in you ideas. I have a GDS and netlist for a design but i don't have the placed and routed DB (DEF or MW) How can i convert the GDS and netlist back to MW/DEF. The...
View ArticleDifference between .ddc and .def files
What is the differences between .ddc and .def files? where these files are created? in Which stage of physical design we use these files?
View ArticleAdvantages and Disadvantages of multi row height cells
Hi All, Can anyone please tell me the exact advantages and disadvantages of multi row height cells when compared with single row height cells. Thanks, Krish.
View ArticleNeed help for hspice simulation using TSMC65 nm
Hello I have a question about using TSMC65 nm in Hspice. I got access to the library recently from school but not sure how I can find the library cells for spice so i can instantiate them in my .sp...
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How to match between the circuit to specificating (including which tests and...
Hello every one, I am new in analog circuit design. I need your help to know how to match the circuit below: to the specification: How to build the circuit and which tests I need to do Please, anyone...
View ArticleDoubt in Placement stage
Hi, After placement stage I checked my timing reports for setup slack. In the capture path I could not see any cells like buff/inv etc. Could anyone please tell why?
View ArticleWhat are the most asked interview questions in Physical Design
What are the most frequently asked physical design interview questions?
View ArticleHi....i want to know how can i reduce the count of buffers and inverters...
Hi....i want to know how can i reduce the count of buffers and inverters introduced during the placeOPt clockOPt or routeOpt stages...
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